20 lines
286 B
Verilog
20 lines
286 B
Verilog
// generated by newgenasym Wed Jul 13 10:11:40 2011
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module adcmp566 (in, \in* , le, \le* , nc, nc2, q, \q* );
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input in;
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input \in* ;
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input le;
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input \le* ;
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inout nc;
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inout nc2;
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output q;
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output \q* ;
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initial
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begin
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end
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endmodule
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