17 lines
435 B
VHDL
17 lines
435 B
VHDL
-- generated by newgenasym Wed Jul 13 10:11:40 2011
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity adcmp566 is
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port (
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\in\: IN STD_LOGIC;
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\in*\: IN STD_LOGIC;
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LE: IN STD_LOGIC;
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\le*\: IN STD_LOGIC;
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NC: INOUT STD_LOGIC;
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NC2: INOUT STD_LOGIC;
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Q: OUT STD_LOGIC;
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\q*\: OUT STD_LOGIC);
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end adcmp566;
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