16 lines
202 B
Verilog
16 lines
202 B
Verilog
// generated by newgenasym Tue Oct 07 16:09:43 2014
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module adg1208 (a, d, en, s);
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input [2:0] a;
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output d;
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input en;
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inout [7:0] s;
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initial
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begin
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end
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endmodule
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