13 lines
337 B
VHDL
13 lines
337 B
VHDL
-- generated by newgenasym Tue Oct 07 16:09:43 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity adg1208 is
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port (
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A: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
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D: OUT STD_LOGIC;
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EN: IN STD_LOGIC;
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S: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0));
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end adg1208;
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