21 lines
567 B
VHDL
21 lines
567 B
VHDL
-- generated by newgenasym Thu Jan 29 16:41:57 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity conn12 is
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port (
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\1\: INOUT STD_LOGIC;
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\10\: INOUT STD_LOGIC;
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\11\: INOUT STD_LOGIC;
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\12\: INOUT STD_LOGIC;
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\2\: INOUT STD_LOGIC;
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\3\: INOUT STD_LOGIC;
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\4\: INOUT STD_LOGIC;
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\5\: INOUT STD_LOGIC;
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\6\: INOUT STD_LOGIC;
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\7\: INOUT STD_LOGIC;
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\8\: INOUT STD_LOGIC;
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\9\: INOUT STD_LOGIC);
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end conn12;
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