39 lines
1.2 KiB
VHDL
39 lines
1.2 KiB
VHDL
-- generated by newgenasym Tue Jan 27 14:33:46 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity conn30 is
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port (
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\1\: IN STD_LOGIC;
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\10\: IN STD_LOGIC;
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\11\: IN STD_LOGIC;
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\12\: IN STD_LOGIC;
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\13\: IN STD_LOGIC;
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\14\: IN STD_LOGIC;
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\15\: IN STD_LOGIC;
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\16\: IN STD_LOGIC;
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\17\: IN STD_LOGIC;
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\18\: IN STD_LOGIC;
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\19\: IN STD_LOGIC;
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\2\: IN STD_LOGIC;
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\20\: IN STD_LOGIC;
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\21\: IN STD_LOGIC;
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\22\: IN STD_LOGIC;
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\23\: IN STD_LOGIC;
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\24\: IN STD_LOGIC;
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\25\: IN STD_LOGIC;
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\26\: IN STD_LOGIC;
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\27\: IN STD_LOGIC;
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\28\: IN STD_LOGIC;
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\29\: IN STD_LOGIC;
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\3\: IN STD_LOGIC;
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\30\: IN STD_LOGIC;
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\4\: IN STD_LOGIC;
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\5\: IN STD_LOGIC;
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\6\: IN STD_LOGIC;
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\7\: IN STD_LOGIC;
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\8\: IN STD_LOGIC;
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\9\: IN STD_LOGIC);
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end conn30;
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