45 lines
816 B
Verilog
45 lines
816 B
Verilog
// generated by newgenasym Wed Jan 28 11:13:39 2015
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module conn32 (\1 , \10 , \11 , \12 , \13 , \14 , \15 , \16 , \17 , \18 , \19 , \2 , \20 , \21 , \22 , \23 , \24 , \25 ,
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\26 , \27 , \28 , \29 , \3 , \30 , \31 , \32 , \4 , \5 , \6 , \7 , \8 , \9 );
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inout \1 ;
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inout \10 ;
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inout \11 ;
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inout \12 ;
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inout \13 ;
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inout \14 ;
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inout \15 ;
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inout \16 ;
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inout \17 ;
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inout \18 ;
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inout \19 ;
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inout \2 ;
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inout \20 ;
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inout \21 ;
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inout \22 ;
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inout \23 ;
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inout \24 ;
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inout \25 ;
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inout \26 ;
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inout \27 ;
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inout \28 ;
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inout \29 ;
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inout \3 ;
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inout \30 ;
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inout \31 ;
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inout \32 ;
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inout \4 ;
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inout \5 ;
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inout \6 ;
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inout \7 ;
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inout \8 ;
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inout \9 ;
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initial
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begin
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end
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endmodule
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