43 lines
1.3 KiB
VHDL
43 lines
1.3 KiB
VHDL
-- generated by newgenasym Fri Jun 20 17:43:26 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity conn34 is
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port (
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\1\: INOUT STD_LOGIC;
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\10\: INOUT STD_LOGIC;
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\11\: INOUT STD_LOGIC;
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\12\: INOUT STD_LOGIC;
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\13\: INOUT STD_LOGIC;
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\14\: INOUT STD_LOGIC;
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\15\: INOUT STD_LOGIC;
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\16\: INOUT STD_LOGIC;
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\17\: INOUT STD_LOGIC;
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\18\: INOUT STD_LOGIC;
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\19\: INOUT STD_LOGIC;
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\2\: INOUT STD_LOGIC;
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\20\: INOUT STD_LOGIC;
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\21\: INOUT STD_LOGIC;
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\22\: INOUT STD_LOGIC;
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\23\: INOUT STD_LOGIC;
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\24\: INOUT STD_LOGIC;
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\25\: INOUT STD_LOGIC;
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\26\: INOUT STD_LOGIC;
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\27\: INOUT STD_LOGIC;
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\28\: INOUT STD_LOGIC;
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\29\: INOUT STD_LOGIC;
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\3\: INOUT STD_LOGIC;
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\30\: INOUT STD_LOGIC;
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\31\: INOUT STD_LOGIC;
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\32\: INOUT STD_LOGIC;
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\33\: INOUT STD_LOGIC;
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\34\: INOUT STD_LOGIC;
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\4\: INOUT STD_LOGIC;
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\5\: INOUT STD_LOGIC;
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\6\: INOUT STD_LOGIC;
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\7\: INOUT STD_LOGIC;
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\8\: INOUT STD_LOGIC;
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\9\: INOUT STD_LOGIC);
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end conn34;
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