25 lines
709 B
VHDL
25 lines
709 B
VHDL
-- generated by newgenasym Mon Aug 2 09:59:21 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity dipswitch is
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port (
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A0: IN STD_LOGIC;
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A1: IN STD_LOGIC;
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A2: IN STD_LOGIC;
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A3: IN STD_LOGIC;
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A4: IN STD_LOGIC;
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A5: IN STD_LOGIC;
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A6: IN STD_LOGIC;
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A7: IN STD_LOGIC;
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B0: OUT STD_LOGIC;
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B1: OUT STD_LOGIC;
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B2: OUT STD_LOGIC;
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B3: OUT STD_LOGIC;
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B4: OUT STD_LOGIC;
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B5: OUT STD_LOGIC;
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B6: OUT STD_LOGIC;
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B7: OUT STD_LOGIC);
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end dipswitch;
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