Something is wrong with the translation block symbol. I'm gonna try and fix it without deleting everything but this commit is just in case i fuck that up
19 lines
505 B
VHDL
19 lines
505 B
VHDL
-- generated by newgenasym Wed Mar 04 12:20:04 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ds90lv019 is
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port (
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DE: IN STD_LOGIC;
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DIN: IN STD_LOGIC;
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DOUT: OUT STD_LOGIC;
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\dout*\: OUT STD_LOGIC;
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GND: IN STD_LOGIC;
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RE: IN STD_LOGIC;
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RI: IN STD_LOGIC;
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\ri*\: IN STD_LOGIC;
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ROUT: OUT STD_LOGIC;
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VCC: IN STD_LOGIC);
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end ds90lv019;
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