12 lines
271 B
VHDL
12 lines
271 B
VHDL
-- generated by newgenasym Mon Sep 13 13:54:04 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ep12sd1sape is
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port (
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CLOSED: OUT STD_LOGIC;
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COMM: IN STD_LOGIC;
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\open\: OUT STD_LOGIC);
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end ep12sd1sape;
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