114 lines
2.0 KiB
Verilog
114 lines
2.0 KiB
Verilog
// generated by newgenasym Mon Oct 4 14:13:30 2010
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module euroconn (a1, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a2, a20,
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a21, a22, a23, a24, a25, a26, a27, a28, a29, a3, a30, a31, a32, a4,
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a5, a6, a7, a8, a9, b1, b10, b11, b12, b13, b14, b15, b16, b17, b18,
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b19, b2, b20, b21, b22, b23, b24, b25, b26, b27, b28, b29, b3, b30,
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b31, b32, b4, b5, b6, b7, b8, b9, c1, c10, c11, c12, c13, c14, c15,
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c16, c17, c18, c19, c2, c20, c21, c22, c23, c24, c25, c26, c27,
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c28, c29, c3, c30, c31, c32, c4, c5, c6, c7, c8, c9);
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inout a1;
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inout a10;
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inout a11;
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inout a12;
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inout a13;
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inout a14;
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inout a15;
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inout a16;
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inout a17;
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inout a18;
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inout a19;
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inout a2;
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inout a20;
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inout a21;
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inout a22;
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inout a23;
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inout a24;
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inout a25;
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inout a26;
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inout a27;
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inout a28;
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inout a29;
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inout a3;
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inout a30;
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inout a31;
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inout a32;
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inout a4;
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inout a5;
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inout a6;
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inout a7;
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inout a8;
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inout a9;
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inout b1;
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inout b10;
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inout b11;
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inout b12;
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inout b13;
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inout b14;
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inout b15;
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inout b16;
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inout b17;
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inout b18;
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inout b19;
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inout b2;
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inout b20;
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inout b21;
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inout b22;
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inout b23;
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inout b24;
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inout b25;
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inout b26;
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inout b27;
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inout b28;
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inout b29;
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inout b3;
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inout b30;
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inout b31;
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inout b32;
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inout b4;
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inout b5;
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inout b6;
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inout b7;
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inout b8;
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inout b9;
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inout c1;
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inout c10;
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inout c11;
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inout c12;
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inout c13;
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inout c14;
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inout c15;
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inout c16;
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inout c17;
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inout c18;
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inout c19;
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inout c2;
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inout c20;
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inout c21;
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inout c22;
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inout c23;
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inout c24;
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inout c25;
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inout c26;
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inout c27;
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inout c28;
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inout c29;
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inout c3;
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inout c30;
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inout c31;
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inout c32;
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inout c4;
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inout c5;
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inout c6;
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inout c7;
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inout c8;
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inout c9;
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initial
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begin
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end
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endmodule
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