119 lines
2.4 KiB
Verilog
119 lines
2.4 KiB
Verilog
// generated by newgenasym Tue Nov 04 12:15:42 2014
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module \fci_61083-101400lf (\1 , \10 , \100 , \101 , \102 , \11 , \12 , \13 , \14 , \15 , \16 , \17 , \18 , \19 , \2 , \20 , \21 ,
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\22 , \23 , \24 , \25 , \26 , \27 , \28 , \29 , \3 , \30 , \31 , \32 , \33 , \34 , \35 , \36 , \37 , \38 ,
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\39 , \4 , \40 , \41 , \42 , \43 , \44 , \45 , \46 , \47 , \48 , \49 , \5 , \50 , \51 , \52 , \53 , \54 ,
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\55 , \56 , \57 , \58 , \59 , \6 , \60 , \61 , \62 , \63 , \64 , \65 , \66 , \67 , \68 , \69 , \7 , \70 ,
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\71 , \72 , \73 , \74 , \75 , \76 , \77 , \78 , \79 , \8 , \80 , \81 , \82 , \83 , \84 , \85 , \86 , \87 ,
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\88 , \89 , \9 , \90 , \91 , \92 , \93 , \94 , \95 , \96 , \97 , \98 , \99 );
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inout \1 ;
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inout \10 ;
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inout \100 ;
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inout \101 ;
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inout \102 ;
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inout \11 ;
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inout \12 ;
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inout \13 ;
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inout \14 ;
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inout \15 ;
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inout \16 ;
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inout \17 ;
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inout \18 ;
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inout \19 ;
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inout \2 ;
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inout \20 ;
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inout \21 ;
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inout \22 ;
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inout \23 ;
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inout \24 ;
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inout \25 ;
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inout \26 ;
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inout \27 ;
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inout \28 ;
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inout \29 ;
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inout \3 ;
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inout \30 ;
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inout \31 ;
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inout \32 ;
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inout \33 ;
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inout \34 ;
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inout \35 ;
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inout \36 ;
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inout \37 ;
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inout \38 ;
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inout \39 ;
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inout \4 ;
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inout \40 ;
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inout \41 ;
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inout \42 ;
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inout \43 ;
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inout \44 ;
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inout \45 ;
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inout \46 ;
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inout \47 ;
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inout \48 ;
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inout \49 ;
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inout \5 ;
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inout \50 ;
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inout \51 ;
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inout \52 ;
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inout \53 ;
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inout \54 ;
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inout \55 ;
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inout \56 ;
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inout \57 ;
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inout \58 ;
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inout \59 ;
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inout \6 ;
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inout \60 ;
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inout \61 ;
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inout \62 ;
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inout \63 ;
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inout \64 ;
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inout \65 ;
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inout \66 ;
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inout \67 ;
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inout \68 ;
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inout \69 ;
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inout \7 ;
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inout \70 ;
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inout \71 ;
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inout \72 ;
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inout \73 ;
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inout \74 ;
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inout \75 ;
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inout \76 ;
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inout \77 ;
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inout \78 ;
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inout \79 ;
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inout \8 ;
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inout \80 ;
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inout \81 ;
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inout \82 ;
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inout \83 ;
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inout \84 ;
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inout \85 ;
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inout \86 ;
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inout \87 ;
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inout \88 ;
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inout \89 ;
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inout \9 ;
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inout \90 ;
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inout \91 ;
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inout \92 ;
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inout \93 ;
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inout \94 ;
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inout \95 ;
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inout \96 ;
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inout \97 ;
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inout \98 ;
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inout \99 ;
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initial
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begin
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end
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endmodule
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