16 lines
240 B
Verilog
16 lines
240 B
Verilog
// generated by newgenasym Mon Aug 2 15:49:02 2010
|
|
|
|
|
|
module \g3vm-352j (ctrl_in, ctrl_out, sig_in, sig_out);
|
|
inout ctrl_in;
|
|
inout ctrl_out;
|
|
input sig_in;
|
|
output sig_out;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|