13 lines
305 B
VHDL
13 lines
305 B
VHDL
-- generated by newgenasym Mon Aug 2 15:49:02 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \g3vm-352j\ is
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port (
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CTRL_IN: INOUT STD_LOGIC;
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CTRL_OUT: INOUT STD_LOGIC;
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SIG_IN: IN STD_LOGIC;
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SIG_OUT: OUT STD_LOGIC);
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end \g3vm-352j\;
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