Tubii_Tk2/Parts/parts/misc/ids_c10/entity/verilog.v
2015-02-27 19:09:38 -05:00

22 lines
345 B
Verilog

// generated by newgenasym Thu Feb 05 11:24:52 2015
module ids_c10 (pin1, pin10, pin2, pin3, pin4, pin5, pin6, pin7, pin8, pin9);
inout pin1;
inout pin10;
inout pin2;
inout pin3;
inout pin4;
inout pin5;
inout pin6;
inout pin7;
inout pin8;
inout pin9;
initial
begin
end
endmodule