43 lines
1.3 KiB
VHDL
43 lines
1.3 KiB
VHDL
-- generated by newgenasym Mon Jan 26 19:02:07 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ids_c34 is
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port (
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PIN1: INOUT STD_LOGIC;
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PIN10: INOUT STD_LOGIC;
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PIN11: INOUT STD_LOGIC;
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PIN12: INOUT STD_LOGIC;
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PIN13: INOUT STD_LOGIC;
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PIN14: INOUT STD_LOGIC;
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PIN15: INOUT STD_LOGIC;
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PIN16: INOUT STD_LOGIC;
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PIN17: INOUT STD_LOGIC;
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PIN18: INOUT STD_LOGIC;
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PIN19: INOUT STD_LOGIC;
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PIN2: INOUT STD_LOGIC;
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PIN20: INOUT STD_LOGIC;
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PIN21: INOUT STD_LOGIC;
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PIN22: INOUT STD_LOGIC;
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PIN23: INOUT STD_LOGIC;
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PIN24: INOUT STD_LOGIC;
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PIN25: INOUT STD_LOGIC;
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PIN26: INOUT STD_LOGIC;
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PIN27: INOUT STD_LOGIC;
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PIN28: INOUT STD_LOGIC;
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PIN29: INOUT STD_LOGIC;
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PIN3: INOUT STD_LOGIC;
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PIN30: INOUT STD_LOGIC;
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PIN31: INOUT STD_LOGIC;
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PIN32: INOUT STD_LOGIC;
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PIN33: INOUT STD_LOGIC;
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PIN34: INOUT STD_LOGIC;
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PIN4: INOUT STD_LOGIC;
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PIN5: INOUT STD_LOGIC;
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PIN6: INOUT STD_LOGIC;
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PIN7: INOUT STD_LOGIC;
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PIN8: INOUT STD_LOGIC;
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PIN9: INOUT STD_LOGIC);
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end ids_c34;
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