Tubii_Tk2/Parts/parts/misc/led_l/entity/verilog.v
2015-02-27 19:09:38 -05:00

14 lines
153 B
Verilog

// generated by newgenasym Fri Jan 30 18:31:33 2015
module led_l (a, b);
inout a;
inout b;
initial
begin
end
endmodule