11 lines
225 B
VHDL
11 lines
225 B
VHDL
-- generated by newgenasym Fri Jan 30 18:31:33 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity led_l is
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port (
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A: INOUT STD_LOGIC;
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B: INOUT STD_LOGIC);
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end led_l;
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