Tubii_Tk2/Parts/parts/misc/lm7171/entity/verilog.v
2015-02-27 19:09:38 -05:00

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244 B
Verilog

// generated by newgenasym Tue Aug 19 14:22:07 2014
module lm7171 (\in+ , \in- , \output , \v+ , \v- );
inout \in+ ;
inout \in- ;
inout \output ;
input \v+ ;
input \v- ;
initial
begin
end
endmodule