Tubii_Tk2/Parts/parts/misc/max9374/entity/verilog.v
2015-02-27 19:09:38 -05:00

20 lines
283 B
Verilog

// generated by newgenasym Wed Oct 15 18:53:03 2014
module max9374 (\1 , \2 , \3 , \4 , \5 , \6 , \7 , \8 );
inout \1 ;
inout \2 ;
inout \3 ;
inout \4 ;
inout \5 ;
inout \6 ;
inout \7 ;
inout \8 ;
initial
begin
end
endmodule