Tubii_Tk2/Parts/parts/misc/max9375/entity/verilog.v
2015-02-27 19:09:38 -05:00

16 lines
213 B
Verilog

// generated by newgenasym Thu Oct 16 16:05:56 2014
module max9375 (in, \in* , out, \out* );
input in;
input \in* ;
output out;
output \out* ;
initial
begin
end
endmodule