13 lines
297 B
VHDL
13 lines
297 B
VHDL
-- generated by newgenasym Thu Oct 16 16:05:56 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity max9375 is
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port (
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\in\: IN STD_LOGIC;
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\in*\: IN STD_LOGIC;
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\out\: OUT STD_LOGIC;
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\out*\: OUT STD_LOGIC);
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end max9375;
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