20 lines
319 B
Verilog
20 lines
319 B
Verilog
// generated by newgenasym Thu Oct 16 19:05:30 2014
|
|
|
|
|
|
module max9376 (in1, \in1* , in2, \in2* , out1, \out1* , out2, \out2* );
|
|
inout in1;
|
|
input \in1* ;
|
|
input in2;
|
|
input \in2* ;
|
|
output out1;
|
|
output \out1* ;
|
|
output out2;
|
|
output \out2* ;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|