16 lines
397 B
VHDL
16 lines
397 B
VHDL
-- generated by newgenasym Wed Oct 22 11:15:01 2014
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use work.all;
|
|
entity opa277 is
|
|
port (
|
|
\in+\: INOUT STD_LOGIC;
|
|
\in-\: INOUT STD_LOGIC;
|
|
\out\: INOUT STD_LOGIC;
|
|
TRIM_A: INOUT STD_LOGIC;
|
|
TRIM_B: INOUT STD_LOGIC;
|
|
\v+\: IN STD_LOGIC;
|
|
\v-\: IN STD_LOGIC);
|
|
end opa277;
|