23 lines
637 B
VHDL
23 lines
637 B
VHDL
-- generated by newgenasym Wed Oct 22 13:49:37 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity opa4277 is
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port (
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\+in_a\: INOUT STD_LOGIC;
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\+in_b\: INOUT STD_LOGIC;
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\+in_c\: INOUT STD_LOGIC;
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\+in_d\: INOUT STD_LOGIC;
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\-in_a\: INOUT STD_LOGIC;
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\-in_b\: INOUT STD_LOGIC;
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\-in_c\: INOUT STD_LOGIC;
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\-in_d\: INOUT STD_LOGIC;
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OUT_A: INOUT STD_LOGIC;
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OUT_B: INOUT STD_LOGIC;
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OUT_C: INOUT STD_LOGIC;
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OUT_D: INOUT STD_LOGIC;
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\v+\: IN STD_LOGIC;
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\v-\: IN STD_LOGIC);
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end opa4277;
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