15 lines
369 B
VHDL
15 lines
369 B
VHDL
-- generated by newgenasym Tue Nov 04 11:56:15 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity prma1c05b is
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port (
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CTRL_IN: INOUT STD_LOGIC;
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CTRL_OUT: INOUT STD_LOGIC;
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\in\: INOUT STD_LOGIC;
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IN_CPY: INOUT STD_LOGIC;
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OUT1: INOUT STD_LOGIC;
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OUT2: INOUT STD_LOGIC);
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end prma1c05b;
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