Tubii_Tk2/Parts/parts/misc/ref02/entity/verilog.v
2015-02-27 19:09:38 -05:00

17 lines
227 B
Verilog

// generated by newgenasym Wed Oct 22 10:44:40 2014
module ref02 (gnd, temp, trim, vin, vout);
input gnd;
inout temp;
inout trim;
inout vin;
inout vout;
initial
begin
end
endmodule