14 lines
327 B
VHDL
14 lines
327 B
VHDL
-- generated by newgenasym Wed Oct 22 10:44:40 2014
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use work.all;
|
|
entity ref02 is
|
|
port (
|
|
GND: IN STD_LOGIC;
|
|
TEMP: INOUT STD_LOGIC;
|
|
TRIM: INOUT STD_LOGIC;
|
|
VIN: INOUT STD_LOGIC;
|
|
VOUT: INOUT STD_LOGIC);
|
|
end ref02;
|