15 lines
180 B
Verilog
15 lines
180 B
Verilog
// generated by newgenasym Thu Jan 29 11:19:37 2015
|
|
|
|
|
|
module ss12sdp2 (p, t_a, t_b);
|
|
inout p;
|
|
inout t_a;
|
|
inout t_b;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|