12 lines
265 B
VHDL
12 lines
265 B
VHDL
-- generated by newgenasym Thu Jan 29 11:19:37 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ss12sdp2 is
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port (
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P: INOUT STD_LOGIC;
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T_A: INOUT STD_LOGIC;
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T_B: INOUT STD_LOGIC);
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end ss12sdp2;
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