15 lines
367 B
VHDL
15 lines
367 B
VHDL
-- generated by newgenasym Wed Jan 28 19:30:00 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ss22sdp2 is
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port (
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P1: INOUT STD_LOGIC;
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P2: INOUT STD_LOGIC;
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T_A1: INOUT STD_LOGIC;
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T_A2: INOUT STD_LOGIC;
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T_B1: INOUT STD_LOGIC;
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T_B2: INOUT STD_LOGIC);
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end ss22sdp2;
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