10 lines
203 B
VHDL
10 lines
203 B
VHDL
-- generated by newgenasym Tue May 18 12:04:11 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity TESTPOINT_L is
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port (
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A: INOUT STD_LOGIC);
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end TESTPOINT_L;
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