243 lines
4.3 KiB
Verilog
243 lines
4.3 KiB
Verilog
// generated by newgenasym Tue Feb 15 11:50:30 2011
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module xc2c512 (a1, a11, a12, a13, a14, a15, a16, a2, a3, a4, a5, a6, a7, a8, a9,
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b1, b10, b11, b12, b13, b14, b15, b16, b2, b3, b4, b5, b6, b7, b8,
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b9, c1, c10, c11, c12, c13, c14, c15, c16, c2, c3, c5, c6, c7, c8,
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c9, cdr1, cdr2, d1, d10, d11, d13, d14, d15, d16, d2, d6, d7, d8,
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d9, dge, e1, e10, e11, e12, e13, e14, e15, e16, e2, e4, e6, e7, e8,
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e9, f1, f12, f13, f14, f15, f16, f2, f3, f5, g1, g11, g12, g13, g14,
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g15, g16, g2, g3, g4, g5, gc1, gc2, goe1, goe2, goe3, goe4, gsr1,
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h1, h12, h13, h14, h15, h16, h2, h3, h4, h5, j1, j12, j13, j14, j15,
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j16, j2, j3, j4, j5, k1, k12, k14, k15, k16, k2, k3, k4, k5, l1, l12,
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l13, l14, l15, l16, l2, l3, l4, l5, m1, m10, m11, m12, m13, m14,
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m15, m16, m4, m5, m6, m7, m8, m9, n1, n10, n11, n13, n14, n15, n16,
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n2, n3, n4, n5, n6, n7, n8, n9, p1, p10, p11, p13, p14, p15, p16, p4,
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p6, p7, p8, p9, r1, r10, r12, r13, r14, r15, r16, r2, r3, r4, r5, r6,
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r7, r8, r9, t1, t10, t11, t12, t13, t14, t15, t16, t2, t3, t4, t6,
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t7, t8, t9, tck, tdi, tdo, tms, vaux);
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inout a1;
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inout a11;
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inout a12;
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inout a13;
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inout a14;
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inout a15;
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inout a16;
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inout a2;
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inout a3;
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inout a4;
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inout a5;
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inout a6;
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inout a7;
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inout a8;
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inout a9;
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inout b1;
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inout b10;
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inout b11;
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inout b12;
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inout b13;
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inout b14;
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inout b15;
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inout b16;
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inout b2;
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inout b3;
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inout b4;
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inout b5;
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inout b6;
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inout b7;
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inout b8;
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inout b9;
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inout c1;
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inout c10;
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inout c11;
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inout c12;
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inout c13;
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inout c14;
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inout c15;
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inout c16;
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inout c2;
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inout c3;
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inout c5;
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inout c6;
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inout c7;
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inout c8;
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inout c9;
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inout cdr1;
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inout cdr2;
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inout d1;
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inout d10;
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inout d11;
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inout d13;
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inout d14;
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inout d15;
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inout d16;
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inout d2;
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inout d6;
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inout d7;
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inout d8;
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inout d9;
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inout dge;
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inout e1;
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inout e10;
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inout e11;
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inout e12;
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inout e13;
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inout e14;
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inout e15;
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inout e16;
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inout e2;
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inout e4;
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inout e6;
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inout e7;
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inout e8;
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inout e9;
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inout f1;
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inout f12;
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inout f13;
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inout f14;
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inout f15;
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inout f16;
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inout f2;
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inout f3;
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inout f5;
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inout g1;
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inout g11;
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inout g12;
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inout g13;
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inout g14;
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inout g15;
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inout g16;
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inout g2;
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inout g3;
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inout g4;
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inout g5;
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inout gc1;
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inout gc2;
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inout goe1;
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inout goe2;
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inout goe3;
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inout goe4;
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inout gsr1;
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inout h1;
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inout h12;
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inout h13;
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inout h14;
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inout h15;
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inout h16;
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inout h2;
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inout h3;
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inout h4;
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inout h5;
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inout j1;
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inout j12;
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inout j13;
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inout j14;
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inout j15;
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inout j16;
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inout j2;
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inout j3;
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inout j4;
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inout j5;
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inout k1;
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inout k12;
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inout k14;
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inout k15;
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inout k16;
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inout k2;
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inout k3;
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inout k4;
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inout k5;
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inout l1;
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inout l12;
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inout l13;
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inout l14;
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inout l15;
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inout l16;
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inout l2;
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inout l3;
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inout l4;
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inout l5;
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inout m1;
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inout m10;
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inout m11;
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inout m12;
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inout m13;
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inout m14;
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inout m15;
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inout m16;
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inout m4;
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inout m5;
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inout m6;
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inout m7;
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inout m8;
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inout m9;
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inout n1;
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inout n10;
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inout n11;
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inout n13;
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inout n14;
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inout n15;
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inout n16;
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inout n2;
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inout n3;
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inout n4;
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inout n5;
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inout n6;
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inout n7;
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inout n8;
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inout n9;
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inout p1;
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inout p10;
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inout p11;
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inout p13;
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inout p14;
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inout p15;
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inout p16;
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inout p4;
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inout p6;
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inout p7;
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inout p8;
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inout p9;
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inout r1;
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inout r10;
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inout r12;
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inout r13;
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inout r14;
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inout r15;
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inout r16;
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inout r2;
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inout r3;
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inout r4;
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inout r5;
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inout r6;
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inout r7;
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inout r8;
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inout r9;
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inout t1;
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inout t10;
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inout t11;
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inout t12;
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inout t13;
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inout t14;
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inout t15;
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inout t16;
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inout t2;
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inout t3;
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inout t4;
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inout t6;
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inout t7;
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inout t8;
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inout t9;
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inout tck;
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inout tdi;
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inout tdo;
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inout tms;
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input vaux;
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initial
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begin
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end
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endmodule
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