226 lines
7.4 KiB
VHDL
226 lines
7.4 KiB
VHDL
-- generated by newgenasym Tue Feb 15 11:50:30 2011
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity XC2C512 is
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port (
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A1: INOUT STD_LOGIC;
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A11: INOUT STD_LOGIC;
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A12: INOUT STD_LOGIC;
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A13: INOUT STD_LOGIC;
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A14: INOUT STD_LOGIC;
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A15: INOUT STD_LOGIC;
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A16: INOUT STD_LOGIC;
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A2: INOUT STD_LOGIC;
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A3: INOUT STD_LOGIC;
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A4: INOUT STD_LOGIC;
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A5: INOUT STD_LOGIC;
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A6: INOUT STD_LOGIC;
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A7: INOUT STD_LOGIC;
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A8: INOUT STD_LOGIC;
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A9: INOUT STD_LOGIC;
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B1: INOUT STD_LOGIC;
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B10: INOUT STD_LOGIC;
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B11: INOUT STD_LOGIC;
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B12: INOUT STD_LOGIC;
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B13: INOUT STD_LOGIC;
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B14: INOUT STD_LOGIC;
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B15: INOUT STD_LOGIC;
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B16: INOUT STD_LOGIC;
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B2: INOUT STD_LOGIC;
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B3: INOUT STD_LOGIC;
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B4: INOUT STD_LOGIC;
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B5: INOUT STD_LOGIC;
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B6: INOUT STD_LOGIC;
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B7: INOUT STD_LOGIC;
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B8: INOUT STD_LOGIC;
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B9: INOUT STD_LOGIC;
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C1: INOUT STD_LOGIC;
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C10: INOUT STD_LOGIC;
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C11: INOUT STD_LOGIC;
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C12: INOUT STD_LOGIC;
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C13: INOUT STD_LOGIC;
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C14: INOUT STD_LOGIC;
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C15: INOUT STD_LOGIC;
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C16: INOUT STD_LOGIC;
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C2: INOUT STD_LOGIC;
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C3: INOUT STD_LOGIC;
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C5: INOUT STD_LOGIC;
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C6: INOUT STD_LOGIC;
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C7: INOUT STD_LOGIC;
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C8: INOUT STD_LOGIC;
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C9: INOUT STD_LOGIC;
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CDR1: INOUT STD_LOGIC;
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CDR2: INOUT STD_LOGIC;
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D1: INOUT STD_LOGIC;
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D10: INOUT STD_LOGIC;
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D11: INOUT STD_LOGIC;
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D13: INOUT STD_LOGIC;
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D14: INOUT STD_LOGIC;
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D15: INOUT STD_LOGIC;
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D16: INOUT STD_LOGIC;
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D2: INOUT STD_LOGIC;
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D6: INOUT STD_LOGIC;
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D7: INOUT STD_LOGIC;
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D8: INOUT STD_LOGIC;
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D9: INOUT STD_LOGIC;
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DGE: INOUT STD_LOGIC;
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E1: INOUT STD_LOGIC;
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E10: INOUT STD_LOGIC;
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E11: INOUT STD_LOGIC;
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E12: INOUT STD_LOGIC;
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E13: INOUT STD_LOGIC;
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E14: INOUT STD_LOGIC;
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E15: INOUT STD_LOGIC;
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E16: INOUT STD_LOGIC;
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E2: INOUT STD_LOGIC;
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E4: INOUT STD_LOGIC;
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E6: INOUT STD_LOGIC;
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E7: INOUT STD_LOGIC;
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E8: INOUT STD_LOGIC;
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E9: INOUT STD_LOGIC;
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F1: INOUT STD_LOGIC;
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F12: INOUT STD_LOGIC;
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F13: INOUT STD_LOGIC;
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F14: INOUT STD_LOGIC;
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F15: INOUT STD_LOGIC;
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F16: INOUT STD_LOGIC;
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F2: INOUT STD_LOGIC;
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F3: INOUT STD_LOGIC;
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F5: INOUT STD_LOGIC;
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G1: INOUT STD_LOGIC;
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G11: INOUT STD_LOGIC;
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G12: INOUT STD_LOGIC;
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G13: INOUT STD_LOGIC;
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G14: INOUT STD_LOGIC;
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G15: INOUT STD_LOGIC;
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G16: INOUT STD_LOGIC;
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G2: INOUT STD_LOGIC;
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G3: INOUT STD_LOGIC;
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G4: INOUT STD_LOGIC;
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G5: INOUT STD_LOGIC;
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GC1: INOUT STD_LOGIC;
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GC2: INOUT STD_LOGIC;
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GOE1: INOUT STD_LOGIC;
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GOE2: INOUT STD_LOGIC;
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GOE3: INOUT STD_LOGIC;
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GOE4: INOUT STD_LOGIC;
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GSR1: INOUT STD_LOGIC;
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H1: INOUT STD_LOGIC;
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H12: INOUT STD_LOGIC;
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H13: INOUT STD_LOGIC;
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H14: INOUT STD_LOGIC;
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H15: INOUT STD_LOGIC;
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H16: INOUT STD_LOGIC;
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H2: INOUT STD_LOGIC;
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H3: INOUT STD_LOGIC;
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H4: INOUT STD_LOGIC;
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H5: INOUT STD_LOGIC;
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J1: INOUT STD_LOGIC;
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J12: INOUT STD_LOGIC;
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J13: INOUT STD_LOGIC;
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J14: INOUT STD_LOGIC;
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J15: INOUT STD_LOGIC;
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J16: INOUT STD_LOGIC;
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J2: INOUT STD_LOGIC;
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J3: INOUT STD_LOGIC;
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J4: INOUT STD_LOGIC;
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J5: INOUT STD_LOGIC;
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K1: INOUT STD_LOGIC;
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K12: INOUT STD_LOGIC;
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K14: INOUT STD_LOGIC;
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K15: INOUT STD_LOGIC;
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K16: INOUT STD_LOGIC;
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K2: INOUT STD_LOGIC;
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K3: INOUT STD_LOGIC;
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K4: INOUT STD_LOGIC;
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K5: INOUT STD_LOGIC;
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L1: INOUT STD_LOGIC;
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L12: INOUT STD_LOGIC;
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L13: INOUT STD_LOGIC;
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L14: INOUT STD_LOGIC;
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L15: INOUT STD_LOGIC;
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L16: INOUT STD_LOGIC;
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L2: INOUT STD_LOGIC;
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L3: INOUT STD_LOGIC;
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L4: INOUT STD_LOGIC;
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L5: INOUT STD_LOGIC;
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M1: INOUT STD_LOGIC;
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M10: INOUT STD_LOGIC;
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M11: INOUT STD_LOGIC;
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M12: INOUT STD_LOGIC;
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M13: INOUT STD_LOGIC;
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M14: INOUT STD_LOGIC;
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M15: INOUT STD_LOGIC;
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M16: INOUT STD_LOGIC;
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M4: INOUT STD_LOGIC;
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M5: INOUT STD_LOGIC;
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M6: INOUT STD_LOGIC;
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M7: INOUT STD_LOGIC;
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M8: INOUT STD_LOGIC;
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M9: INOUT STD_LOGIC;
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N1: INOUT STD_LOGIC;
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N10: INOUT STD_LOGIC;
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N11: INOUT STD_LOGIC;
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N13: INOUT STD_LOGIC;
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N14: INOUT STD_LOGIC;
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N15: INOUT STD_LOGIC;
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N16: INOUT STD_LOGIC;
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N2: INOUT STD_LOGIC;
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N3: INOUT STD_LOGIC;
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N4: INOUT STD_LOGIC;
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N5: INOUT STD_LOGIC;
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N6: INOUT STD_LOGIC;
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N7: INOUT STD_LOGIC;
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N8: INOUT STD_LOGIC;
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N9: INOUT STD_LOGIC;
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P1: INOUT STD_LOGIC;
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P10: INOUT STD_LOGIC;
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P11: INOUT STD_LOGIC;
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P13: INOUT STD_LOGIC;
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P14: INOUT STD_LOGIC;
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P15: INOUT STD_LOGIC;
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P16: INOUT STD_LOGIC;
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P4: INOUT STD_LOGIC;
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P6: INOUT STD_LOGIC;
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P7: INOUT STD_LOGIC;
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P8: INOUT STD_LOGIC;
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P9: INOUT STD_LOGIC;
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R1: INOUT STD_LOGIC;
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R10: INOUT STD_LOGIC;
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R12: INOUT STD_LOGIC;
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R13: INOUT STD_LOGIC;
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R14: INOUT STD_LOGIC;
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R15: INOUT STD_LOGIC;
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R16: INOUT STD_LOGIC;
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R2: INOUT STD_LOGIC;
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R3: INOUT STD_LOGIC;
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R4: INOUT STD_LOGIC;
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R5: INOUT STD_LOGIC;
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R6: INOUT STD_LOGIC;
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R7: INOUT STD_LOGIC;
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R8: INOUT STD_LOGIC;
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R9: INOUT STD_LOGIC;
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T1: INOUT STD_LOGIC;
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T10: INOUT STD_LOGIC;
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T11: INOUT STD_LOGIC;
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T12: INOUT STD_LOGIC;
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T13: INOUT STD_LOGIC;
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T14: INOUT STD_LOGIC;
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T15: INOUT STD_LOGIC;
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T16: INOUT STD_LOGIC;
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T2: INOUT STD_LOGIC;
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T3: INOUT STD_LOGIC;
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T4: INOUT STD_LOGIC;
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T6: INOUT STD_LOGIC;
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T7: INOUT STD_LOGIC;
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T8: INOUT STD_LOGIC;
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T9: INOUT STD_LOGIC;
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TCK: INOUT STD_LOGIC;
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TDI: INOUT STD_LOGIC;
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TDO: INOUT STD_LOGIC;
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TMS: INOUT STD_LOGIC;
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VAUX: IN STD_LOGIC);
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end XC2C512;
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