46 lines
1.4 KiB
VHDL
46 lines
1.4 KiB
VHDL
-- generated by newgenasym Fri Dec 17 19:09:48 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity XC2C64A is
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port (
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IO1: INOUT STD_LOGIC;
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IO10: INOUT STD_LOGIC;
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IO11: INOUT STD_LOGIC;
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IO12: INOUT STD_LOGIC;
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IO13: INOUT STD_LOGIC;
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IO14: INOUT STD_LOGIC;
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IO15: INOUT STD_LOGIC;
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IO16: INOUT STD_LOGIC;
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IO17: INOUT STD_LOGIC;
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IO18: INOUT STD_LOGIC;
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IO19: INOUT STD_LOGIC;
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IO2: INOUT STD_LOGIC;
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IO20: INOUT STD_LOGIC;
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IO21: INOUT STD_LOGIC;
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IO22: INOUT STD_LOGIC;
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IO23: INOUT STD_LOGIC;
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IO24: INOUT STD_LOGIC;
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IO25: INOUT STD_LOGIC;
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IO26: INOUT STD_LOGIC;
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IO27: INOUT STD_LOGIC;
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IO28: INOUT STD_LOGIC;
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IO29: INOUT STD_LOGIC;
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IO3: INOUT STD_LOGIC;
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IO30: INOUT STD_LOGIC;
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IO31: INOUT STD_LOGIC;
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IO32: INOUT STD_LOGIC;
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IO33: INOUT STD_LOGIC;
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IO4: INOUT STD_LOGIC;
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IO5: INOUT STD_LOGIC;
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IO6: INOUT STD_LOGIC;
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IO7: INOUT STD_LOGIC;
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IO8: INOUT STD_LOGIC;
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IO9: INOUT STD_LOGIC;
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TCK: IN STD_LOGIC;
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TDI: IN STD_LOGIC;
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TDO: OUT STD_LOGIC;
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TMS: INOUT STD_LOGIC);
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end XC2C64A;
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