16 lines
216 B
Verilog
16 lines
216 B
Verilog
// generated by newgenasym Mon Oct 20 17:01:19 2014
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module pot (a, b, c);
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parameter size = 1;
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inout [size-1:0] a;
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inout [size-1:0] b;
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inout c;
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initial
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begin
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end
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endmodule
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