13 lines
277 B
VHDL
13 lines
277 B
VHDL
-- generated by newgenasym Tue May 18 12:00:45 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity CONN_GEN is
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generic (
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size:positive:= 1
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);
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port (
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CON_PIN: INOUT STD_LOGIC_VECTOR (size-1 DOWNTO 0));
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end CONN_GEN;
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