8 lines
147 B
VHDL
8 lines
147 B
VHDL
-- generated by newgenasym Tue May 18 12:01:03 2010
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use work.all;
|
|
entity ORIGIN is
|
|
end ORIGIN;
|