15 lines
174 B
Verilog
15 lines
174 B
Verilog
// generated by newgenasym Tue May 18 12:05:02 2010
|
|
|
|
|
|
module mmbth81lt1 (b, c, e);
|
|
input b;
|
|
inout c;
|
|
inout e;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|