Tubii_Tk2/Parts/parts/ttl/74f07/entity/verilog.v
2015-02-27 19:09:38 -05:00

24 lines
345 B
Verilog

// generated by newgenasym Tue Aug 31 12:02:08 2010
module \74f07 (a0, a1, a2, a3, a4, a5, y0, y1, y2, y3, y4, y5);
input a0;
input a1;
input a2;
input a3;
input a4;
input a5;
output y0;
output y1;
output y2;
output y3;
output y4;
output y5;
initial
begin
end
endmodule