21 lines
569 B
VHDL
21 lines
569 B
VHDL
-- generated by newgenasym Tue Aug 31 12:02:08 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \74f07\ is
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port (
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A0: IN STD_LOGIC;
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A1: IN STD_LOGIC;
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A2: IN STD_LOGIC;
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A3: IN STD_LOGIC;
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A4: IN STD_LOGIC;
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A5: IN STD_LOGIC;
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Y0: OUT STD_LOGIC;
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Y1: OUT STD_LOGIC;
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Y2: OUT STD_LOGIC;
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Y3: OUT STD_LOGIC;
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Y4: OUT STD_LOGIC;
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Y5: OUT STD_LOGIC);
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end \74f07\;
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