21 lines
569 B
VHDL
21 lines
569 B
VHDL
-- generated by newgenasym Fri Sep 17 14:15:51 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \74f14\ is
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port (
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I0: IN STD_LOGIC;
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I1: IN STD_LOGIC;
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I2: IN STD_LOGIC;
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I3: IN STD_LOGIC;
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I4: IN STD_LOGIC;
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I5: IN STD_LOGIC;
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\o0*\: IN STD_LOGIC;
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\o1*\: IN STD_LOGIC;
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\o2*\: IN STD_LOGIC;
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\o3*\: IN STD_LOGIC;
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\o4*\: IN STD_LOGIC;
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\o5*\: IN STD_LOGIC);
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end \74f14\;
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