19 lines
276 B
Verilog
19 lines
276 B
Verilog
// generated by newgenasym Wed Jul 16 16:49:56 2014
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module \74fhct597 (d, ds, \mr* , \pl* , q, shcp, stcp);
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input [7:0] d;
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input ds;
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input \mr* ;
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input \pl* ;
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output q;
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input shcp;
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input stcp;
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initial
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begin
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end
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endmodule
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