16 lines
427 B
VHDL
16 lines
427 B
VHDL
-- generated by newgenasym Wed Jul 16 16:49:56 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \74fhct597\ is
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port (
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D: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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DS: IN STD_LOGIC;
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\mr*\: IN STD_LOGIC;
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\pl*\: IN STD_LOGIC;
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Q: OUT STD_LOGIC;
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SHCP: IN STD_LOGIC;
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STCP: IN STD_LOGIC);
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end \74fhct597\;
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