24 lines
383 B
Verilog
24 lines
383 B
Verilog
// generated by newgenasym Wed Aug 20 15:56:21 2014
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module \74hct04 (a0, a1, a2, a3, a4, a5, \y0* , \y1* , \y2* , \y3* , \y4* , \y5* );
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input a0;
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input a1;
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input a2;
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input a3;
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input a4;
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input a5;
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output \y0* ;
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output \y1* ;
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output \y2* ;
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output \y3* ;
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output \y4* ;
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output \y5* ;
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initial
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begin
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end
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endmodule
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