21 lines
573 B
VHDL
21 lines
573 B
VHDL
-- generated by newgenasym Wed Aug 20 15:56:21 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \74hct04\ is
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port (
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A0: IN STD_LOGIC;
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A1: IN STD_LOGIC;
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A2: IN STD_LOGIC;
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A3: IN STD_LOGIC;
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A4: IN STD_LOGIC;
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A5: IN STD_LOGIC;
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\y0*\: OUT STD_LOGIC;
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\y1*\: OUT STD_LOGIC;
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\y2*\: OUT STD_LOGIC;
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\y3*\: OUT STD_LOGIC;
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\y4*\: OUT STD_LOGIC;
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\y5*\: OUT STD_LOGIC);
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end \74hct04\;
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