26 lines
734 B
VHDL
26 lines
734 B
VHDL
-- generated by newgenasym Wed Oct 29 14:26:38 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity f06 is
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generic (
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size:positive:= 1
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);
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port (
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A: IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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A0: IN STD_LOGIC;
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A1: IN STD_LOGIC;
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A2: IN STD_LOGIC;
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A3: IN STD_LOGIC;
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A4: IN STD_LOGIC;
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A5: IN STD_LOGIC;
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\y*\: OUT STD_LOGIC_VECTOR (size-1 DOWNTO 0);
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\y0*\: OUT STD_LOGIC;
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\y1*\: OUT STD_LOGIC;
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\y2*\: OUT STD_LOGIC;
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\y3*\: OUT STD_LOGIC;
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\y4*\: OUT STD_LOGIC;
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\y5*\: OUT STD_LOGIC);
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end f06;
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