13 lines
276 B
Verilog
13 lines
276 B
Verilog
// generated by genview Thu Jan 15 20:26:26 1998
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`timescale 1ns/100ps
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module f06 (a, \y* );
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parameter size = 1;
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input [size-1:0] a;
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output [size-1:0] \y* ;
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SIG74F06P inst1[size-1:0] (/*.D0*/ a,
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/*.Q0_*/ \y* );
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endmodule |