17 lines
467 B
VHDL
17 lines
467 B
VHDL
-- generated by newgenasym Wed Jul 16 15:07:13 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity f269 is
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port (
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CEP: IN STD_LOGIC;
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CET: IN STD_LOGIC;
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CP: IN STD_LOGIC;
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P: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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PE: IN STD_LOGIC;
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Q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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TC: OUT STD_LOGIC;
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\u/d\: IN STD_LOGIC);
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end f269;
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